In recent years, the research and development on nonvolatile storage devices including memory cells using variable resistance elements has been conducted. The variable resistance element is an element having characteristics in which a resistance value reversibly changes based on an electrical signal, and capable of storing data corresponding to the resistance value with nonvolatility.
What is generally known as a nonvolatile storage device using such variable resistance elements is a nonvolatile storage device including 1T1R memory cells arranged in a matrix. Each of the memory cells includes a MOS transistor and a variable resistance element that are connected in series, at an intersection point between (i) a bit line and (ii) a word line and a source line, where the lines cross at right angles.
Furthermore, in order to further develop integrated circuits, there has been an increase in the research on cross-point nonvolatile storage devices each including diode elements and variable resistance elements that are connected in series, at intersection points between bit lines and word lines that cross at right angles.
PTL 1 discloses memory cells each including (i) a variable resistance element that stores and holds information according to an electric resistance state and (ii) a circuit element connected in series with the variable resistance element. With application of a voltage and a current to the memory cell, the variable resistance element can have a resistance value that reversibly changes between a low resistance state and a high resistance state.
FIG. 19 illustrates a circuit diagram of a memory cell C used in a storage device disclosed in PTL 1. The memory cell C includes a variable resistance element A and a circuit element T which are electrically connected in series with each other. The variable resistance element A has a structure including a storage layer between two electrodes (for example, upper electrode and lower electrode), and the storage layer includes an amorphous thin film, such as a rare-earth metal oxide film. PTL 1 discloses that the rare-earth metal oxide film comprises metals that can be easily ionized, such as Cu, Ag, and Zn. Furthermore, the circuit element T includes a Metal-Insulator-Semiconductor (MIS) transistor. The MIS transistor serves as an active element that controls access to the variable resistance element A, with application of a predetermined voltage VGS to a gate terminal of the transistor. It also serves as a load device for the variable resistance element A. When the circuit element is in an ON state, the resistance value of the variable resistance element A can be changed with application of a predetermined voltage and a current to end terminals V1 and V2 of the memory cell C.
FIG. 20 illustrates changes in voltage and current of the variable resistance element A disclosed in PTL 1. Assuming that the operation of changing resistance of the variable resistance element A from a high resistance state to a low resistance state is a writing operation and the operation of changing resistance of the variable resistance element A from the low resistance state to the high resistance state is an erasing operation, the variable resistance element A initially has a large resistance value and is in a state where current is hard to flow (ST1). Then, with application of a write threshold voltage or higher (+1.1×[V]), the current flows and the resistance value is being decreased (ST2). Then, the variable resistance element A exhibits Ohmic characteristics (ST3), and the current flows in proportion to the voltage. Afterward, even when the voltage becomes 0 V, the variable resistance element A continues to hold the low resistance value. Next, when a negative voltage is being applied to the variable resistance element A and the application voltage is being increased, the current decreases with application of an erase threshold voltage (−1.1×[V]) (ST4). Then, the resistance of the variable resistance element A is changed to resistance as same as that in the erase state. Afterward, even when the voltage becomes 0 V, the variable resistance element A continues to hold the high resistance value (ST5).
FIG. 21 illustrates changes in an operating point of the variable resistance element A disclosed in PTL 1. The vertical axis represents the current [A] that flows through an MIS transistor T corresponding to the circuit element T and the variable resistance element A, and the horizontal axis represents the voltage [V] that is applied to the MIS transistor T and the variable resistance element A. In the graph, dashed lines represent the voltage/current characteristics when the gate voltage of the MIS transistor T is changed to VG1, VG2, and VG3 (VG1>VG2>VG3), while solid lines represent the voltage/current characteristics of the variable resistance element A in the low and high resistance states. The high resistance state is represented to overlap the horizontal axis.
As indicated by the solid lines in FIG. 21, the resistance state of the variable resistance element A is changed from the high resistance state to the low resistance state, with application of the voltage Vth (approximately 0.52 V) between the electrodes of the variable resistance element A by applying the voltage V (1.0 V) between the end terminals V1 and V2 of the memory cell C. Here, the graph indicates that the resistance value of the variable resistance element A is determined according to a value of the current that flows through the variable resistance element A through the MIS transistor T. For example, when the gate voltage is VG1, the current flows up to an operating point P1 indicating the highest current. The resistance value calculated based on the relationship between the voltage and the current at the operating point P1 is a resistance value of the variable resistance element A in the low resistance state. Similarly, when the gate voltage is VG2, the current flows up to an operating point P2 where the resistance state is high. When the gate voltage is VG3, the current flows up to an operating point P3 where the resistance state is much higher. Thus, the graph indicates that the resistance values calculated based on the relationship between the voltage and the current at the respective operating points P2 and P3 are resistance values of the variable resistance element A in the low resistance state.
In other words, controlling (i) the voltage to be applied to the end terminals of the memory cell C including the variable resistance element A and the MIS transistor T and (ii) the gate voltage of the MIS transistor T enables controlling of the resistance value of the variable resistance element A in the low resistance state. PTL 1 discloses the storage device capable of recording multi-valued data using this feature.
Next, PTL 2 discloses a storage device that achieves stable operations with application of a uniform voltage to each memory cell in a memory cell array. Between the voltage application circuit that applies a write voltage to the memory cells and the memory cells, long metal lines such as bit lines exist. When the memory cell closer to the voltage application circuit is accessed in the case of performing the writing operation for the low resistance state, the voltage drop caused by the line resistance is small. Thus, a large amount of current can flow, and the resistance state of the memory cell is changed to the low resistance state having a lower resistance value. On the other hand, when the memory cell distant from the voltage application circuit is accessed, the voltage drop caused by the line resistance is large. Thus, the amount of current that flows decreases, and the resistance state of the memory cell is changed to the low resistance state having a resistance value higher than that of the former case.
In other words, PTL 2 suggests the technique to solve the problems that a resistance value in the low resistance state to be written in the memory cell depends on a place where the memory cell is arranged and the uniform operation cannot be performed.
FIG. 22 illustrates, as a solution disclosed in PTL 2, a structure including (i) drivers each of which applies a predetermined voltage to a bit line connected to a terminal of another bit line, and (ii) operational amplifiers each of which adjusts the voltage applied by the driver to the bit line by comparing, with a preset voltage, the voltage to be applied to a memory element positioned to the other end of the bit line.